1131_Digital Logic Design_335063
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Course Period：Now ~ Any Time
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Course Intro
Course Resources
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0_9月9日(一)上午1010~1200 新生開學典禮(不上課)
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1_syllabus_LogicDesign
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2_Silde_passwd_ntutld
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3_Ch1
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4_CH1_Assignment
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4-2_Please use stapler to staple your submitted homework if having muliple papers
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5_Ch2
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6_CH2_Assignment
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Classroom on Thursday is changed to 二教301
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7_Ch3
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8_CH3_Assignment
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Nov.7(Thursday) 1010am_Midterm
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期中考_11月7日(四)_原上課教室(10am先在走廊等候，重新排座位)。範圍_到10月28日內容(10月31日颱風放假))。
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Nov.4(Mon.) without course
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期中考週_11月4日(一)_不上課，請自行溫書
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9-1_Ch4
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9-2_Quartus II 8.1 Web Edition_installation_simulation
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9-3_Quartus II 8.1 Web Edition_used_new
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9-5_CH4_Assignment
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10_Ch5
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11_Ch5_Quartus II 8.1_VHDL_Majority_Vote
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CH5_QuartusII_VHDL_Assignment
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12_Ch6
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13_CH6_Assignment
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14_Ch7
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15_CH7_Assignment
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12月19日(四)數位邏設 第二堂要小考(範圍CH6 P1-P50)
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Jan.6(Mon.) without course
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Final_Exam_Jan.9(Thursday.) 1010am_Range(CH4~2025.Jan.2)
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[錄] 09121016
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[錄] 09121418
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[錄] 09161011
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[錄] 09191010
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[錄] 09231015
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[錄] 09261013
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[錄] 09301012
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[錄] 10071011
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[錄] 10141011
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[錄] 10171011
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[錄] 10211010
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[錄] 10241012
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[錄] 10281012
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[錄] 11111010
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[錄] 11141010
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[錄] 11181009
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[錄] 11211007
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[錄] 11251010
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[錄] 11251112
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[錄] 11281008
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[錄] 12021007
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[錄] 12051012
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[錄] 12091007
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[錄] 12121008
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[錄] 12191009
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[錄] 12191308
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[錄] 12231010
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[錄] 12261010
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[錄] 12301038
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[錄] 01021009
Teacher / 王多柏
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